Electrical Engineering ⇒ Topic : Representation of Logic Expression
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David
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REPRESENTATION OF LOGIC EXPRESSION Let us consider a logic expression Y = AB + AC. In this expression, A, B and C are literals. A literal is a primed or unprimed variable. When a Boolean function is implemented with logic gates, each literal in the function designates an input to the gate. It is required to minimize the literals and the number of terms, so that we can implement a logic function with less number of gates. The literals and terms are generally arranged in one of the two standard forms:
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