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Definition of "dual phase-locked loop (DPLL)" |
programmable, low-jitter, low-power, and high-performance devices. DPPLs are capable of synthesizing two low-jitter clocks with user-selected, industry-standard frequencies, phased-locked to the system reference timing. They accept a wide range of popular telecom and networking input frequencies and can be programmed to generate a range of output frequencies. Used for wide area network (WAN) and ISDN applications. |
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