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Definition of "pipelined cache" |
a cache memory with a latency of several clock cycles that supports one new access every cycle. A new access can be started even before finishing a previous one. The access to the cache is divided into several stages whose operation can be overlapped. For instance, the cache can be pipelined to speed up write accesses: tags and data are stored in independently addressable modules so that the next tag comparison can be overlapped with the current write access. Read accesses are performed in a single cycle (tag and data read at the same time). |
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