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Definition of "reduced instruction set computer (RISC) processor" |
relatively simple control unit design with a reduced menu of instructions (selected to be simple), data and instructions formats, addressing modes, and with a uniform streamlined handling of pipelines. One of the particular features of a RISC processor is the restriction that all memory accesses should be by load and store instructions only (the so called load/store architecture). All operations in a RISC are registerto- register, meaning that both the sources and destinations of all operations are CPU registers. All this tends to significantly reduce CPU to memory data traffic, thus improving performance. In addition, RISCs usually have the following properties: most instructions execute within a single cycle, all in structions have the same standard size (32 bits), the control unit is hardwired (to increase speed of operations), and there is a CPU register file of considerable size (32 registers in most systems, with the exception of SPARC with 136 and AMD 29000 with 192 registers). |
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