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Definition of "super pipelined processor" |
a processor where more than one instruction is fetched during a cycle in a staggered manner. That is, in an n-issue superpipelined processor, an instruction is fetched every 1=n of a cycle. For example, in the MIPS R4000, which is two-issue superpipeline, a new instruction is fetched every half cycle. Thus, in effect, the instruction pipeline runs at a frequency double than the system (in the R4000 the pipeline frequency is 100 MHz, while the external frequency is 50 MHz). Superpipeline processors usually have a relatively deep pipeline, of about 7 stages or more (8 stages on the R4000). |
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